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| NCP1081 Integrated High Power PoE-PD Interface & DC-DC Converter Controller Introduction The NCP1081 is a member of ON Semiconductor's high power HIPOt Power over Ethernet Powered Device (PoE-PD) product family and represents a robust, flexible and highly integrated solution targeting demanding medium and high power Ethernet applications. It combines in a single unit an enhanced PoE-PD interface supporting the IEEE802.3af and the upcoming draft IEEE802.3at (D3.0) standard TSSOP-20 EP and a flexible and configurable DC-DC converter controller. DE SUFFIX The NCP1081's exceptional capabilities offer new opportunities for CASE 948AB the design of products powered directly over Ethernet lines, eliminating the need for local power adaptors or power supplies and drastically reducing the overall installation and maintenance cost. ON Semiconductor's unique manufacturing process and design enhancements allow the NCP1081 to deliver up to 25.5 W for the draft IEEE802.3at (D3.0) standard and up to 40 W for proprietary high power PoE applications. The NCP1081 enables the draft IEEE802.3at (D3.0) and implements a two event physical layer classification. Additional proprietary classification procedures support high power power sourcing equipment (PSE) on the market. The unique high power features leverage the significant cost advantages of PoE-enabled systems to a much broader spectrum of products in emerging markets such as industrial ethernet devices, PTZ and Dome NCP1081 = Specific Device Code IP cameras, RFID readers, MIMO WLAN access points, high end XXXX = Date Code VoIP phones, notebooks, etc. Y = Assembly Location The integrated current mode DC-DC controller facilitates isolated ZZ = Traceability Code and non-isolated fly-back, forward and buck converter topologies. It has all the features necessary for a flexible, robust and highly efficient ORDERING INFORMATION design including programmable switching frequency, duty cycle up to See detailed ordering and shipping information in the package 80 percent, slope compensation, and soft start-up. dimensions section on page 2 of this data sheet. The NCP1081 is fabricated in a robust high voltage process and integrates a rugged vertical N-channel DMOS with a low loss current sense technique suitable for the most * Extended power ranges up to 40 W demanding environments and capable of withstanding harsh * Programmable classification current environments such as hot swap and cable ESD events. * Adjustable under voltage lock out The NCP1081 complements ON Semiconductor's ASSP * Programmable inrush current limit portfolio in industrial devices and can be combined with * Programmable operational current limit up to 1100 mA stepper motor drivers, CAN bus drivers and other for extended power ranges high-voltage interfacing devices to offer complete solutions to the industrial and security market. * Over-temperature protection * Industrial temperature range -40C to 85C with full Powered Device Interface operation up to 150C junction temperature * Supporting the IEEE802.3af and the upcoming draft * 0.6 ohm hot-swap pass-switch with low loss current IEEE802.3at (D3.0) standard sense technique * Supports draft IEEE802.3at (D3.0) Two Event Layer 1 * Vertical N-channel DMOS pass-switch offers the classification robustness of discrete MOSFETs with integrated * High power Layer 1 classification indicator temperature control (c) Semiconductor Components Industries, LLC, 2008 http://onsemi.com September, 2008 - Rev. 4 1 Publication Order Number: NCP1081/D NCP1081 DC-DC Converter Controller * Current mode control * Supports isolated and non-isolated DC-DC converter * Internal voltage regulators * Wide duty cycle range with internal slope * Programmable oscillator frequency * Programmable soft-start time Ordering Information Part Number NCP1081DEG NCP1081DER2G Package TSSOP-20 EP (Pb-Free) TSSOP-20 EP (Pb-Free) PIN DIAGRAM VPORTP CLASS UVLO INRUSH ILIM1 VPORTN1 RTN VPORTN2 TEST1 TEST2 1 SS FB COMP VDDL VDDH GATE ARTN nCLASS_AT CS OSC applications compensation circuitry Exposed Pad (Top View) Shipping Configuration 74 units / Tube 2500 / Tape & Reel Temperature Range -40C to 85C -40C to 85C For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. VPORTP DETECTION INTERNAL SUPPLY & BANDGAP THERMAL SHUT DOWN VDDH VDDH VDDL VDDL CLASS CLASSIFICATION VDDL VDDL 5 mA SS UVLO UVLO VPORT MONITOR DC-DC CONVERTER CONTROL VDDL 5 K 1.2 V FB COMP CS INRUSH ILIM1 INRUSH ILIM1 OSC HOT SWAP SWITCH CONTROL & CURRENT LIMIT BLOCKS VDDL 20 mA VDDH OSC GATE nCLASS_AT ARTN VPORTN1,2 RTN Figure 1. NCP1081 Block Diagram http://onsemi.com 2 NCP1081 Simplified Application Diagrams RJ- 45 Rclass VPORTP CLASS VDDH Cvddh Cpd T1 D1 Voutput Z_line DB1 Cline Data Pairs Rinrush INRUSH VDDL NCP1081 nCLASS_AT GATE CS FB ARTN RTN Cvddl LD1 Cload Rd1 M1 Rilim1 R1 ILIM1 UVLO R2 TEST2 TEST1 VPORTN1 COMP OSC VPORTN2 SS Rslope Rcs R5 OC1 C2 Optocoupler R3 C1 Spare Pairs DB2 Rosc Css Z1 R4 Figure 2. Isolated Fly-back Converter Figure 2 shows the integrated PoE-PD switch and DC-DC controller configured to work in a fully isolated application. The output voltage regulation is accomplished with an external opto-coupler and a shunt regulator (Z1). VPORTP Rclass Cpd RJ- 45 CLASS VDDH T1 Cvddh Voutput Z_line DB1 Cline Data Pairs Rinrush INRUSH VDDL NCP1081 nCLASS_AT Cvddl LD1 Rd1 M1 R3 Cload Rilim1 R1 ILIM1 UVLO R2 GATE CS FB ARTN RTN COMP OSC SS TEST2 TEST1 VPORTN1 VPORTN2 Rslope R4 Rcs Spare Pairs DB2 Css Rosc C1comp Rcomp C2comp Figure 3. Non-Isolated Fly-back Converter Figure 3 shows the integrated PoE-PD and DC-DC controller configured in a non-isolated fly-back configuration. A compensation network is inserted between the FB and the COMP pin for overall stability of the feedback loop. http://onsemi.com 3 NCP1081 Simplified Application Diagrams D2 T1 RJ-45 Rclass VPORTP CLASS VDDH R5 D1 Cpd Voutput Z_line DB1 Cline Data Pairs Rinrush INRUSH Cvddh VDDL NCP1081 nCLASS_AT Cvddl LD1 Cload Rd1 R3 M1 Rilim1 R1 ILIM1 UVLO R2 TEST2 TEST1 COMP VPORTN1 VPORTN2 OSC SS GATE CS FB ARTN RTN Rslope R4 Rcs Spare Pairs DB2 Css Rosc C1comp Rcomp C2comp Figure 4. Non-Isolated Fly-back with Extra Winding Figure 4 shows the same non-isolated fly-back configuration as Figure 3, but adds a 12 V auxiliary bias winding on the transformer to provide power to the NCP1081 DC-DC controller via its VDDH pin. This topology shuts off the current flowing from VPORTP to VDDH and therefore reduces the internal power dissipation of the PD, resulting in higher overall power efficiency. D3 Cpd T1 L1 RJ- 45 VPORTP Rclass D1 Voutput CLASS VDDH Cvddh D2 R3 Z_line DB1 Cline Data Pairs Rinrush INRUSH VDDL NCP1081 nCLASS_AT Cvddl LD1 Cload Rd1 M1 Rilim1 R1 ILIM1 UVLO R2 GATE CS FB ARTN RTN COMP OSC SS TEST2 TEST1 VPORTN1 VPORTN2 Rslope R4 Rcs Spare Pairs DB2 Css Rosc C1comp Rcomp C2comp Figure 5. Non-Isolated Forward Converter Figure 5 shows the NCP1081 used in a non-isolated forward topology. High Power Considerations The NCP1081 is designed to implement various configurations of high-power PoE systems including those based on the developing IEEE 802.3at standard. High power operation can be enabled by a Dual Event Layer 1 classification or a Single Event Layer 1 classification combined with a Layer 2 high power classification. The NCP1081 also supports proprietary designs capable of delivering 25 W to 40 W to the load in two-pair configurations. A separate application note describes these implementations ("NCP1081 High Power PoE Applications"). http://onsemi.com 4 NCP1081 Table 1. Pin Descriptions Name VPORTP VPORTN1 VPORTN2 RTN ARTN VDDH Pin No. 1 6,8 7 14 16 Type Supply Ground Ground Ground Supply Description Positive input power. Voltage with respect to VPORTN1,2. Negative input power. Connected to the source of the internal pass-switch. DC-DC controller power return. Connected to the drain of the internal pass-switch. It must be connected to ARTN. This pin is also the drain of the internal pass-switch. DC-DC controller ground pin. Must be connected to RTN as a single point ground connection for improved noise immunity. Output of the 9 V LDO internal regulator. Voltage with respect to ARTN. Supplies the internal gate driver. VDDH must be bypassed to ARTN with a 1 mF or 2.2 mF ceramic capacitor with low ESR. Output of the 3.3 V LDO internal regulator. Voltage with respect to ARTN. This pin can be used to bias an external low-power LED (1 mA max.) connected to nCLASS_AT, and can also be used to add extra biasing current in the external opto-coupler. VDDL must be bypassed to ARTN with a 330 nF or 470 nF ceramic capacitor with low ESR. Classification current programming pin. Connect a resistor between CLASS and VPORTN1,2. Inrush current limit programming pin. Connect a resistor between INRUSH and VPORTN1,2. Operational current limit programming pin. Connect a resistor between ILIM1 and VPORTN1,2. DC-DC controller under-voltage lockout input. Voltage with respect to VPORTN1,2. Connect a resistor-divider from VPORTP to UVLO to VPORTN1,2 to set an external UVLO threshold. DC-DC controller gate driver output pin. Internal oscillator frequency programming pin. Connect a resistor between OSC and ARTN. Active-low, open-drain Layer 1 dual-finger classification indicator. Output of the internal error amplifier of the DC-DC controller. COMP is pulled-up internally to VDDL with a 5 kW resistor. In isolated applications, COMP is connected to the collector of the opto-coupler. Voltage with respect to ARTN. DC-DC controller inverting input of the internal error amplifier. In isolated applications, the pin should be strapped to ARTN to disable the internal error amplifier. Current-sense input for the DC-DC controller. Voltage with respect to ARTN. Soft-start input for the DC-DC controller. A capacitor between SS and ARTN determines the soft-start timing. Digital test pin must always be connected to VPORTN1,2. Digital test pin must always be connected to VPORTN1,2. Exposed pad. Connected to VPORTN1,2 ground. VDDL 17 Supply CLASS INRUSH ILIM1 UVLO GATE OSC nCLASS_AT COMP 2 4 5 3 15 11 13 18 Input Input Input Input Output Input Output, Open Drain I/O FB CS SS TEST1 TEST2 EP 19 12 20 9 10 Input Input Input Input Input http://onsemi.com 5 NCP1081 Table 2. Absolute Maximum Ratings Symbol VPORTP RTN ARTN VDDH VDDL CLASS INRUSH ILIM1 UVLO OSC COMP FB CS SS nCLASS_AT TEST1 TEST2 Ta Tj Tj-TSD Tstg TJA ESD-HBM ESD-CDM ESD-MM LU ESD-SYS Parameter Input power supply Analog ground supply 2 Internal regulator output Internal regulator output Analog output Analog output Analog output Analog input Analog output Analog input / output Analog input Analog input Analog input Analog output Digital inputs Ambient temperature Junction temperature Junction temperature (Note 1) Storage Temperature Thermal Resistance, Junction to Air (Note 2) Human Body Model Charged Device Model Machine Model Latch-up System ESD (contact/air) (Note 3) 3.5 750 300 200 8/15 Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 - - -55 Max. 72 72 17 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 3.6 85 150 175 150 37.6 - - - - - Units V V V V V V V V V V V V V V V C C C C C/W kV V V mA kV per JEDEC Standard JESD78 Exposed pad connected to VPORTN1,2 ground per MIL-STD-883, Method 3015 Thermal shutdown condition Conditions Voltage with respect to VPORTN1,2 Pass-switch in off-state (Voltage with respect to VPORTN1,2) Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to VPORTN1,2 Voltage with respect to VPORTN1,2 Voltage with respect to VPORTN1,2 Voltage with respect to VPORTN1,2 Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to ARTN Voltage with respect to VPORTN1,2 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Tj-TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour cumulative during the useful life for reliability reasons. 2. Mounted on a 1S2P (3 layer) test board with copper coverage of 25 percent for the signal layers and 90 percent copper coverage for the inner planes at an ambient temperature of 85C in still air. Refer to JEDEC JESD51-7 for details. 3. Surges per EN61000-4-2, 1999 applied between RJ-45 and output ground and between adapter input and output ground of the evaluation board. The specified values are the test levels and not the failure levels. http://onsemi.com 6 NCP1081 Recommended Operating Conditions Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the recommended operating conditions for extended periods of time may affect device reliability. All values concerning the DC-DC controller, VDDH, VDDL, and nCLASS_AT blocks are with respect to ARTN. All others are with respect to VPORTN1,2 (unless otherwise noted). Table 3. Operating Conditions Symbol INPUT SUPPLY VPORT Input supply voltage 0 57 V VPORT = VPORTP - VPORTN1,2 Parameter Min. Typ. Max. Units Conditions SIGNATURE DETECTION Vsignature Rsignature Offset_current Sleep_current CLASSIFICATION Vcl V_mark I_mark dR_mark Vreset Iclass0 Iclass1 Iclass2 Iclass3 Iclass4 Iclass5 IDCclass Input supply voltage classification range Mark event voltage range (VPORTP falling) Current consumption I(VPORTP) + I(Rdet) in Mark Event range Input signature during Mark Event (Note 7) Classification Reset range (VPORTP falling) Class 0: Rclass 10 kW (Note 6) Class 1: Rclass 130 ohm (Note 6) Class 2: Rclass 69.8 ohm (Note 6) Class 3: Rclass 44.2 ohm (Note 6) Class 4: Rclass 30.9 ohm (Note 6) Class 5: Rclass 22.1 ohm (Notes 5 and 6) (for proprietary high power applications) Internal current consumption during classification (Note 8) 13 5.4 0.5 - 4.3 0 9 17 26 36 50 - - - - 4.9 - - - - - - 600 20.5 9.7 2.0 12 5.4 4 12 20 30 44 60 - V V mA kW V mA mA mA mA mA mA mA Iclass0 = I_VportP + I_Rdet Iclass1 = I_VportP + I_Rdet Iclass2 = I_VportP + I_Rdet Iclass3 = I_VportP + I_Rdet Iclass4 = I_VportP + I_Rdet Iclass5 = I_VportP + I_Rdet For information only 5.4 V VPORT 9.5 V For information only Input supply voltage signature detection range Signature resistance (Note 4) I_VportP + I_Rtn I_VportP + I_Rtn 1.4 23.75 - - 1.8 15 9.5 26.25 5 25 V kW mA mA VPORTP = RTN = 1.4 V VPORTP = RTN = 9.5 V CLASSIFICATION INDICATOR nCLASS_AT_i NCLASS_AT_pd nCLASS_AT current source NCLASS_AT pull down resistance 13 20 130 27 mA ohm For information only 4. Test done according to the IEEE 802.3af 2 Point Measurement. The minimum probe voltages measured at the PoE-PD are 1.4 V and 2.4 V, and the maximum probe voltages are 8.5 V and 9.5 V. 5. This extended classification range can be used with a PSE which also uses this classification range to deliver more current than specified by IEEE 802.3. 6. Measured with an external Rdet of 25.5 kW between VPORTP and VPORTN1,2, and for 13 V < VPORT < 20.5 V (with VPORT = VPORTP - VPORTN1,2). 7. Measured with the 2 Point Measurement defined in the IEEE 802.3af standard with 5.4 V and 9.5 V the extreme values for V2 and V1. 8. This typical current excludes the current in the Rclass and Rdet external resistors. http://onsemi.com 7 NCP1081 Table 3. Operating Conditions Symbol UVLO Vuvlo_on Vuvlo_off Vhyst_int Vuvlo_pr Default turn on voltage (VportP rising) Default turn off voltage (VportP falling) UVLO internal hysteresis UVLO external programming range - 29.5 - 25 38 32 6 - 40 - - 50 V V V V UVLO pin tied to VPORTN1,2 UVLO pin tied to VPORTN1,2 UVLO pin tied to VPORTN1,2 UVLO pin connected to the resistor divider (R1 & R2). For information only UVLO pin connected to the resistor divider (R1 & R2) For information only Parameter Min. Typ. Max. Units Conditions Vhyst_ext Uvlo_Filter UVLO external hysteresis UVLO on/off filter time - - 15 90 - - % mS ohm mA mA mA mA mA mA PASS-SWITCH AND CURRENT LIMITS Ron I_Rinrush1 I_Rinrush2 I_Rilim1 I_Rilim2 I_Rilim3 I_Rilim4 Pass-switch Rds-on Rinrush = 150 kW (Note 9) Rinrush = 57.6 kW (Note 9) Rilim1 = 84.5 kW (Note 9) Rilim1 = 66.5 kW (Note 9) Rilim1 = 55.6 kW (Note 9) Rilim1 = 38.3 kW (Note 9) - 95 260 450 600 720 970 0.6 125 310 510 645 770 1100 1.2 155 360 570 690 820 1230 Max Ron specified at Tj = 130C Measured at RTN- VPORTN1,2 = 3 V Measured at RTN- VPORTN1,2 = 3 V Current limit threshold Current limit threshold Current limit threshold Current limit threshold INRUSH AND ILIM1 CURRENT LIMIT TRANSITION Vds_pgood VDS required for power good status 0.8 1 1.2 V RTN-VPORTN1,2 falling; Voltage with respect to VPORTN1,2 Voltage with respect to VPORTN1,2 Vds_pgood_hyst VDS hysteresis required for power good status - 8.2 - V 9. The current value corresponds to the PoE-PD input current (the current flowing in the external Rdet and the quiescent current of the device are included). http://onsemi.com 8 NCP1081 Table 3. Operating Conditions Symbol VDDH REGULATOR VDDH_reg Regulator output voltage (Notes 10 and 11) Ivddh_load + Ivddl_load < 10 mA with 0 < Ivddl_load < 2.25 mA Regulator turn-off voltage VDDH regulator current limit (Notes 10 and 11) VDDH POR level (rising) VDDH POR level (falling) VDDH over-voltage level (rising) 8.4 9 9.6 V Parameter Min. Typ. Max. Units Conditions VDDH_Off VDDH_lim VDDH_Por_R VDDH_Por_F VDDH_ovlo VDDL REGULATOR VDDL_reg - 13 7.3 6 16 VDDH_reg + 0.5 V - - - - - 26 8.3 7 18.5 V mA V V V For information only Regulator output voltage (Notes 10 and 11) 0 < lvddl_load < 2.25 mA with lvddh_load + Ivddl_load < 10 mA VDDL POR level (rising) VDDL POR level (falling) 3.05 3.3 3.55 V VDDL_Por_R VDDL_Por_F GATE DRIVER Gate_Tr Gate_Tf VDDL - 0.2 2.5 - - VDDL - 0.02 2.9 V V GATE rise time (10-90%) GATE fall time (90-10%) - - - - 50 50 ns ns Cload = 2 nF, VDDHreg = 9 V Cload = 2 nF, VDDHreg = 9 V PWM COMPARATOR VCOMP ERROR AMPLIFIER Vbg_fb Av_ol GBW SOFT-START Vss Vss_r Iss Soft-start voltage range Soft-start low threshold (rising edge) Soft-start source current - 0.35 3 1.15 0.45 5 - 0.55 7 V V mA Reference voltage DC open loop gain Error amplifier GBW 1.15 - 1 1.2 80 - 1.25 - - V dB MHz Voltage with respect to ARTN For information only For information only COMP control voltage range 1.3 - 3 V For information only CURRENT LIMIT COMPARATOR CSth Tblank OSCILLATOR DutyC Frange F_acc Maximum duty cycle Oscillator frequency range Oscillator frequency accuracy - 100 80% - 25 - 500 kHz % Fixed internally CS threshold voltage Blanking time 324 - 360 100 396 - mV nS For information only 10. Power dissipation must be considered. Load on VDDH and VDDL must be limited especially if VDDH is not powered by an auxiliary winding. 11. Ivddl_load = current flowing out of the VDDL pin. Ivddh_load = current flowing out of the VDDH pin + current delivered to the Gate Driver (function of the frequency, VDDH voltage & MOSFET gate capacitance). http://onsemi.com 9 NCP1081 Table 3. Operating Conditions Symbol CURRENT CONSUMPTION IvportP1 IvportP2 VPORTP internal current consumption (Note 12) VPORTP internal current consumption (Note 13) - - 2.5 4.7 3.5 6.5 mA mA DC-DC controller off DC-DC controller on Parameter Min. Typ. Max. Units Conditions THERMAL SHUTDOWN TSD Thyst Thermal shutdown threshold Thermal hysteresis 150 - - 15 - - C Tj C Tj Tj = junction temperature Tj = junction temperature THERMAL RATINGS Ta Tj Ambient temperature Junction temperature -40 - - - 85 125 150 C C C Parametric values guaranteed Max 1000 hours 12. Conditions a. No current through the pass-switch b. DC-DC controller inactive (SS shorted to RTN) c. No external load on VDDH and VDDL d. VPORTP = 57 V 13. Conditions a. No current through the pass-switch b. Oscillator frequency = 100 kHz c. No external load on VDDH and VDDL d. Aux winding not used e. 2 nF on GATE, DC-DC controller enabled f. VPORTP = 57 V http://onsemi.com 10 NCP1081 Description of Operation Powered Device Interface The PD interface portion of the NCP1081 supports the IEEE 802.3af and draft IEEE802.3at (D3.0) defined operating modes: detection signature, current source classification, inrush, and operating current limits. In order to give more flexibility to the user and also to keep control of the power dissipation in the NCP1081, both current limits are configurable. The device enters operation once its programmable Vuvlo_on threshold is reached, and operation ceases when the supplied voltage falls below the Vuvlo_off threshold. Sufficient hysteresis and Uvlo filter time are provided to avoid false power on/off cycles due to transient voltage drops on the cable. Detection During the detection phase, the incremental equivalent resistance seen by the PSE through the cable must be in the IEEE 802.3af standard specification range (23.75 kW to 26.25 kW) for a PSE voltage from 2.7 V to 10.1 V. In order to compensate for the non-linear effect of the diode bridge and satisfy the specification at low PSE voltage, the NCP1081 presents a suitable impedance in parallel with the 25.5 kW Rdet external resistor. For some types of diodes (especially Schottky diodes), it may be necessary to adjust this external resistor. When the Detection_Off level is detected (typically 11.5 V) on VPORTP, the NCP1081 turns on its internal 3.3 V regulator and biasing circuitry in anticipation of the classification phase as the next step. Classification The NCP1081 can handle all defined types of classification, IEEE 802.3af, draft IEEE802.3at (D3.0) and proprietary classification. In the IEEE 802.3af standard the classification is performed with a Single Event Layer 1 classification. Depending on the current level set during that single event the power level is determined. The current draft IEEE802.3at (D3.0) allows two ways of classification which can also be combined. These two approaches enable higher power applications through a variety of PSE equipment. For power injectors and midspans a pure physical hardware handshake is introduced called Two Event Layer 1 classification. This approach allows equipment that has no data link between PSE and PD to classify as high power. Since switches can establish a data link between PSE and PD, a software handshake is possible. This type of handshake is called Layer 2 classification (or Data Link Layer classification). It has the main advantage of having a finer power resolution and the ability for the PSE and PD to participate in dynamic power allocation. Table 4. Single and Dual Event Classification Standard 802.3af 802.3at 802.3at Layer 1 1 2 Handshake Single event physical classification Two event physical classification Data-link (IP) communication classification Once the PSE device has detected the PD device, the classification process begins. The NCP1081 is fully capable of responding and completing all classification handshaking procedures as described next. Classification Current Source Generation One Event Layer 1 Classification An IEEE 802.3af compliant PSE performs only One Event Layer 1 classification event by increasing the line voltage into the classification range only once. Two Event Layer 1 Classification In classification, the PD regulates a constant current source that is set by the external resistor RCLASS value on the CLASS pin. Figure 6 shows the schematic overview of the classification block. The current source is defined as: I class + VPORTP V bg R class , (where V bg is 1.2 V) VDDA1 1.2 V CLASS Rclass VPORTN1,2 NCP1081 A draft IEEE802.3at (D3.0) compliant PSE using this physical classification performs two classification events and looks for the appropriate response from the PD to check if the PD is draft IEEE802.3at (D3.0) compatible. The PSE will generate the sequence described in Figure 7. During the first classification finger, the PSE will measure the classification current which should be 40 mA if the PD is at compliant. If this is the case, the PSE will exit the classification range and will force the line voltage into the Mark Event range. Within this range, the PSE may check the non-valid input signature presented by the PD (using the two point measurement defined in the IEEE 802.3af standard). Then the PSE will repeat the same sequence with the second classification finger. A PD which has detected the sequence "Finger + Mark + Finger + Mark" knows the PSE is draft IEEE802.3at (D3.0) compliant, meaning the PSE will deliver more current on the port. (Note that a PSE draft Figure 6. Classification Block Diagram http://onsemi.com 11 NCP1081 IEEE802.3at (D3.0) compliant may apply more than two fingers, but the final result will be the same as two fingers). UVLO_on 20.5 V Class range 13 V 9.5 V Mark Range 5.4 V 1st Class Event 1st Mark Event 2nd Class Event 2nd Mark Event Reset Range 0V 2 Fingers Classification with Mark Events (.at spec) Operation Mode: Detection Number of Mark Event: X PSE Type identification: 0 1 2 PSE identified as type 2 PSE (at) Power On PSE identified by default as type 1 PSE (af) Figure 7. Hardware Physical Classification Event Sequence nCLASS_AT Indicator The nCLASS_AT active low open drain output pin can be used to notify to the microprocessor of the powered device that the PSE performed a one or two event hardware classification. If a two event hardware classification has occured and once the PD application is supplied power by the NCP1081 DC-DC converter, the nCLASS_AT pin will be pulled down to ARTN by the internal low voltage NMOS switch (ARTN is the ground connection of the DC-DC converter). Otherwise, nCLASS_AT will be disabled and will be pulled up to VDDL (3.3V typ) via an internal current source (20 mA typ) and via the external pull-up resistor. The following scheme illustrates how the nCLASS_AT pin may be configured with the processor of the powered device. An opto-coupler is used to guarantee full isolation between the Ethernet cable and the application. Powered Device Application Csup VDDL VDDL 20uA Rled Rbip IN1 Microprocessor or Microcontroller VSUP Layer 2 Engine nCLASS_AT Class_AT ARTN NCP1081 IN2 Opto 1 Features GND Isolation (Isolated DC/DC converter) Figure 8. Isolated nClass_AT Communication with the Powered Device Application http://onsemi.com 12 NCP1081 As soon as the application is powered by the DC-DC converter and completes initialization, the microprocessor should check if the NCP1081 detected a two event hardware classification by reading its digital input (pin IN1 in this example). If pin IN1 is low, the application knows power is supplied by a draft IEEE802.3at (D3.0) compliant PSE, and can deliver power up to the level specified by the draft IEEE802.3at (D3.0) standard. Otherwise the application will have to perform a Layer 2 classification with the PSE. There are several scenarios for which the NCP1081 will not enable its nCLASS_AT pin: * The PSE skipped the classification phase. * The PSE performed a one event hardware classification (it can be a IEEE 802.3af or a draft IEEE802.3at (D3.0) compliant PSE with Layer 2 engine). * The PSE performed a two event hardware classification but it did not properly control the input voltage in the mark voltage window, (for example it crossed the reset range). Power Mode To define the UVLO threshold externally, the UVLO pin must be connected to the center of an external resistor divider between VPORTP and VPORTN1,2 as shown in Figure 10. The series resistance value of the external resistors must add to 25.5 kW and replaces the internal signature resistor. VPORTP R1 VPORT UVLO R2 VPORTN1,2 NCP1081 Figure 10. External UVLO Configuration When the classification hand-shake is completed, the PSE and PD devices move into the operating mode. Under Voltage Lock Out (UVLO) For a Vuvlo_on desired turn-on voltage threshold, R1 and R2 can be calculated using the following equations: R1 ) R2 + R det R2 + 1.2 V ulvo_on R det The NCP1081 incorporates an under voltage lock out (ULVO) circuit which monitors the input voltage and determines when to apply power to the DC-DC controller. To use the default settings for UVLO (see Table 3), the pin UVLO must be connected to VPORTN1,2. In this case the signature resistor has to be placed directly between VPORTP and VPORTN1,2, as shown in Figure 9. VPORTP When using the external resistor divider, the NCP1081 has an external reference voltage hysteresis of 15 percent typical. Inrush and Operational Current Limitations The inrush current limit and the operational current limit are programmed individually by an external Rinrush and Rilim1 resistors respectively connected between INRUSH and VPORTN1,2, and between ILIM1 and VPORTN1,2 as shown in Figure 11. VPORT Rdet UVLO VPORTN1,2 NCP1081 Figure 9. Default UVLO Settings http://onsemi.com 13 NCP1081 VDDA1 VDDA1 ILIM1 / INRUSH Vbg1 Ilim_ref VPORTNx NCP1081 Figure 11. Current Limitation Configuration (Inrush & Ilim1 Pins) Inrush Ilim1 0 1 I_pass_switch & VDS_PGOOD detector Current_limit_ON VDDA1 Vds_pgood threshold 1V / 9.2V VPORTNx VDDA1 VDDA1 2V Pass Switch NCP1081 RTN Figure 12. Inrush and Ilim1 Selection Mechanism When VPORT reaches the UVLO_on level, the Cpd capacitor is charged with the INRUSH current (in order to limit the internal power dissipation of the pass-switch). Once the Cpd capacitor is fully charged, the current limit switches from the inrush current to the current limit level (ilim1) as shown in Figure 12. This transition occurs when both following conditions are satisfied: 1. The VDS of the pass-switch is below the Vds_pgood low level (1 V typical). 2. The pass-switch is no longer in current limit mode, meaning the gate of the pass-switch is "high" (above 2 V typical). The operational current limit will stay selected as long as Vds_pgood is true (meaning that RTN-VPORTN1,2 is below the high level of Vds_pgood). This mechanism allows a current level transition without any current spike in the pass-switch because the operational current limit (ilim1) is enabled once the pass-switch is not limiting the current anymore, meaning that the Cpd capacitor is fully charged. Thermal Shutdown The NCP1081 includes thermal protection which shuts down the device in case of high power dissipation. Once the thermal shutdown (TSD) threshold is exceeded, following blocks are turned off: * DC-DC controller * Pass-switch * VDDH and VDDL regulators * CLASS regulator When the TSD error disappears and if the input line voltage is still above the UVLO level, the NCP1081 automatically restarts with the current limit set in the inrush state, the DC-DC controller is disabled and the Css (soft-start capacitor) discharged. The DC-DC controller becomes operational as soon as capacitor Cpd is fully charged. http://onsemi.com 14 NCP1081 DC-DC Converter Controller The NCP1081 implements a current mode DC-DC converter controller which is illustrated in Figure 13. OSC VDDL 5 kW Oscillator Reset CLK Set CLK 3.3 V LDO COMP Current Slope Compensation 10 mA 0 PWM comp CS Blanking time VDDL 360 mV 5 mA SS Soft-start 11 kW 2 Current limit comp 1.45 V R ARTN S Q Gate Driver 9 V LDO VDDH VDDL VPORTP 1.2 V FB GATE Figure 13. DC-DC Controller Block Diagram Internal VDDH and VDDL Regulators and Gate Driver An internal linear regulator steps down the VPORTP voltage to a 9 V output on the VDDH pin. VDDH supplies the internal gate driver circuit which drives the GATE pin and the gate of the external power MOSFET. The NCP1081 gate driver supports an external MOSFET with high Vth and high input gate capacitance. A second LDO regulator steps down the VDDH voltage to a 3.3 V output on VDDL. VDDL powers the analog circuitry of the DC-DC controller and nCLASS_AT blocks. Moreover it can provide current to light a LED connected on the nCLASS_AT pin. In order to prevent uncontrolled operations, both regulators include power-on-reset (POR) detectors which prevent the DC-DC controller from operating when either VDDH or VDDL is too low. In addition, an over-voltage lockout (OVLO) on the VDDH supply disables the gate driver in case of an open-loop converter with a configuration using the bias winding of the transformer (see Figure 4). Both VDDH and VDDL regulators turn on as soon as VPORT reaches the Vuvlo_on threshold. Error Amplifier In isolated topologies the error amplifier is not used because it is already implemented externally with the shunt regulator on the secondary side of the DC-DC controller (see Figure 2). Therefore the FB pin must be strapped to ARTN and the output transistor of the opto-coupler has to be connected on the COMP pin where an internal 5 kW pull-up resistor is tied to the VDDL supply (see Figure 13). Soft-Start In non-isolated converter topologies, the high gain internal error amplifier of the NCP1081 and the internal 1.2 V reference voltage regulate the DC-DC output voltage. In this configuration, the feedback loop compensation network should be inserted between the FB and COMP pins as shown in Figures 3, 4 and 5. The soft-start function provided by the NCP1081 allows the output voltage to ramp up in a controlled fashion, eliminating output voltage overshoot. This function is programmed by connecting a capacitor Css between the SS and ARTN pins. While the DC-DC controller is in POR, the capacitor Css is fully discharged. After coming out of POR, an internal current source of 5 mA typically starts charging the capacitor Css to initiate soft-start. When the voltage on SS pin has reached 0.45 V (typical), the gate driver is enabled and DC-DC operation starts with a duty cycle limit which increases with the SS pin voltage. The soft-start function is finished when the SS pin voltage goes above 1.6 V for which the duty cycle limit reaches its maximum value of 80 percent. Soft-start can be programmed by using the following equation: tss(ms) + 0.23 Css(nf) http://onsemi.com 15 NCP1081 Current Limit Comparator The NCP1081 current limit block behind the CS pin senses the current flowing in the external MOSFET for current mode control and cycle-by-cycle current limit. This is performed by the current limit comparator which, on the CS pin, senses the voltage across the external Rcs resistor located between the source of the MOSFET and the ARTN pin. The NCP1081 also provides a blanking time function on CS pin which ensures that the current limit and PWM comparators are not prematurely trigged by the current spike that occurs when the switching MOSFET turns on. Slope Compensation Circuitry conduction mode (CCM) and when the duty cycle is close or above 50 percent, the NCP1081 integrates a current slope compensation circuit. The amplitude of the added slope compensation is typically 110 mV over one cycle. As an example, for an operating switching frequency of 250 kHz, the internal slope provided by the NCP1081 is 27.5 mV/mA typically. DC-DC Controller Oscillator The frequency is configured with the Rosc resistor inserted between OSC and ARTN, and is defined by the following equation: R OSC(kW) + 38600 F OSC(kHz) To overcome sub-harmonic oscillations and instability problems that exist with converters running in continuous The duty cycle limit is fixed internally at 80 percent. http://onsemi.com 16 NCP1081 PACKAGE DIMENSIONS TSSOP-20 EP CASE 948AB-01 ISSUE O D B 20 B DETAIL B 11 0.20 C A-B D 2X 10 TIPS e/2 DETAIL B E1 E b b1 D 10 20X PIN 1 REFERENCE c c1 1 e A b 0.10 M SECTION B-B NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.07 IN EXCESS OF THE LEAD WIDTH AT MMC. DAMBAR CANNOT BE LOACTED ON THE LOWER RADIUS OR THE FOOT OF THE LEAD. 4. DIMENSIONS b, b1, c, c1 TO BE MEASURED BETWEEN 0.10 AND 0.25 FROM LEAD TIP. 5. DATUMS A AND B ARE ARE DETERMINED AT DATUM H. DATUM H IS LOACTED AT THE MOLD PARTING LINE AND COINCIDENT WITH LEAD WHERE THE LEAD EXITS THE PLASTIC BODY. 6. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.15 PER SIDE. DIMENSION E1 DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.15 PER SIDE. D AND E1 ARE DETERMINED AT DATUM H. DIM A A1 A2 b b1 c c1 D E E1 e L L2 M P P1 MILLIMETERS MAX MIN --1.10 0.05 0.15 0.85 0.95 0.19 0.30 0.19 0.25 0.09 0.20 0.09 0.16 6.40 6.60 6.40 BSC 4.30 4.50 0.65 BSC 0.50 0.70 0.25 BSC 0_ 8_ --4.20 --3.00 TOP VIEW 0.05 C C A-B D B A2 A B C SEATING PLANE 0.08 C 20X SIDE VIEW P A1 H L2 GAUGE PLANE SEATING PLANE P1 BOTTOM VIEW *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. The product described herein may be covered by one or more US patents pending. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative http://onsemi.com 17 IIII IIII IIII L DETAIL A 6.76 20X EEE EEE EEE M DETAIL A END VIEW C SOLDERING FOOTPRINT* 4.30 3.10 0.98 0.65 PITCH 0.35 DIMENSIONS: MILLIMETERS 20X NCP1081/D |
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